The invention relates, in general, to non-volatile memory structures and more particularly to the Electrically Erasable Programmable Read Only Memory (hereinafter abbreviated as EEPROM) structures and erasing methods for EEPROM devices on Silicon-on-Insulator (hereinafter abbreviated as SOI) substrates (films).
EEPROMs are a recent addition to the class of non-volatile memories. They are similar to conventional UV EEPROMs, but can be programmed and erased electrically, thus eliminating the need for UV light sources and window packages. EEPROMs use a dual-layer polysilicon gate technology to permanently store charge as exemplified in U.S. Pat. No. 3,984,822 (One Transistor approach), and in U.S. Pat. No. 4,412,311 (Step Gate approach). Floating gate technology is used for the lower-layer polysilicon to store charge that makes the memory cell conducting or non-conducting, thus implementing a logical "1" or "0". The EEPROM cell is usually programmed by charging the floating gate via hot-electron injection from the drain's pinch-off region as described in the "Background of the Invention" of U.S. Pat. No. 4,888,734, which is herein incorporated by reference. The EEPROM cell is usually erased by Fowler-Nordheim (hereinafter abbreviated as F-N) tunneling of the electrons out of the floating gate, as exemplified in U.S. Pat. No. 4,004,159.
The floating gate family of devices are usually inversion mode devices whereby source and drain regions of one conductivity type are formed on a substrate of the opposite conductivity type. Depletion mode devices are also possible, where source, drain, and substrate are all of the same conductivity type. Between the source and drain regions, and on the surface of the substrate, a gate structure is created by first forming a thin oxide layer on the surface of the substrate between the source and the drain regions (the channel region). A conductive layer is then placed over the insulating layer and constitutes the floating gate. A second insulating layer is then formed over the floating gate to completely surround the floating gate and insulate it from the remainder of the device followed by a second conductive layer called the control gate which is formed atop of the insulating layer. Such devices fabricated on standard, bulk silicon substrates are exemplified in U.S. Pat. Nos. 3,984,822, and 4,412,311.
The subject invention relates to the EEPROM structures on SOI substrates and erasing schemes for such devices. There are several examples of EEPROM devices fabricated on SOI substrates as exemplified in U.S. Pat. Nos. 4,162,504, 4,297,719, 4,876,582, and in Japanese Patent 04-25077. None of these references, however, incorporates a back control gate. EEPROMs fabricated on conventional silicon substrates that make use of two separate control gates have been described in the prior art, but both of these gates were located on the top of the device. Additionally, the operation of both of them was based on F-N tunneling, as exemplified in U.S. Pat. No. 4,099,196, and as opposed to hot carrier injection as in the subject invention.
Various methods to erase information in EEPROM devices have been proposed in the prior art. Majority of these methods are based on F-N tunneling of carriers out of the floating gate. They are exemplified by the following methods: High voltage Source with grounded gate Erase (HSE), Negative Gate with positive Source Erase (NGSE), Negative Gate with grounded Channel Erase (NGCE), as described in the article Yoshikawa et al,"Comparison of Current Flash EEPROM Erasing Methods: Stability and How to Control", 1992,1992 IEDM Conference Proceedings, 595-598. F-N tunneling of the carriers out of the floating gate leads to large distribution of threshold voltage after erase, slow erasing speed and interface degradation.
The control of the erased cell threshold voltage is the key issue, because when a programmed cell is read, if there are over-erased cells with negative threshold voltage on the accessed bit line, a read error occurs. Some approaches to solving this problem have been reported as described in the article Yamada et al, "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM",1991, 1991 IEDM Conference Proceedings, pp. 307-310. In one of the approaches, erase and verify sequences are iterated and to obtain a tight distribution of threshold voltage, a pre-program for all bytes is carried out, and the gradual erase and verify sequence is being iterated until the threshold voltages for all bytes in the array are less than or equal to the desired value. Another approach is to reduce the oxide-ridge on the silicon-dioxide surface by reducing the phosphorous in the floating gate and lowering the annealing temperature after forming the floating gate. In an additional approach, a method known as the self convergence erasing scheme is employed. This method makes use of the avalanche hot carrier injection after erasure by F-N tunneling wherein the threshold voltages converge to a certain steady-state value as a result of the injection. The steady state value is caused by a balance between the avalanche hot electron injection into the floating gate and the avalanche hot hole injection into the floating gate. The erasing sequence eliminates the need for the pre-program and iteration of the erase and verify sequences. However, this process is slow because both F-N tunneling and avalanche hot carrier injection have to be used sequentially. In a different approach as exemplified in U.S. Pat. No. 4,884,239, which is based solely on the hot carrier injection and not on the F-N tunneling, the injection of hot carriers into the floating gate is achieved from a generated reverse avalanche current between the EEPROM drain and substrate.
All methods to erase information in the EEPROM devices described above have inherent shortcomings of large electric fields across the gate dioxide and/or along the front channel and/or problems with the erased threshold voltage distribution and/or erase speed, that are overcome by the subject invention, described hereinbelow.